1. Field of the Invention
The invention relates to a testing device, and more particularly to a testing device using a feedback signal to determine the test result.
2. Description of the Related Art
After a chip is manufactured, the chip undergoes testing to determine whether the chip functions. Complete testing, however, is time consuming, thus, a simplified testing procedure is frequently employed. The simplified test procedure comprises inputting a test signal to the chip and determining whether the output signal via the corresponding pin is correct. FIG. 1 is a block diagram of a conventional chip testing device. The chip testing device 11 comprises a plurality of chip testing units 15, and each chip testing unit comprises a flip-flop unit 12 and an AND gate 13. The flip-flop unit 12 receives an output signal from one pin of a chip, and the output terminal of the flip-flop unit 12 is coupled to a display device 14 and an input terminal of the AND gate 13, wherein another input terminal of the AND gate 13 receives a control signal S1, and the output terminal of the AND gate 13 is coupled to an input terminal of the AND gate of another testing unit, and the output terminal of the last AND gate outputs an output signal S2. When chip testing device 11 operates, the pin of the chip outputs a logic high signal, thus, the output signal of flip-flop unit 12 is also a logic high signal. The output signal of the AND gate 13 is a logic high signal in response to the control signal S1 being a logic high signal. According to the testing mechanism, if the output signal S2 is not at logic high level, there must be at least one pin outputting an incorrect signal. The signal S2, however, is not able to identify faulty pins. The only way to identify faults depends on the state of the display device 14. In one embodiment, the display device 14 is a light emitting diode (LED) or any device that can represent two logic states. In the testing device illustrated in FIG. 1, if the display device 14 does not emit light, this means that the corresponding pin is not outputting a logic high signal. In FIG. 1, the testing device requires a plurality of AND gates, and the size of the circuit area corresponds to the number of pins of the chip. The chip testing mechanism illustrated in FIG. 1 is not actually able to identify the location of the faulty pins, thus, the potential application of the chip testing device is limited.
FIG. 2 is a block diagram of another conventional chip testing device. The chip testing device 11 comprises a plurality of chip testing units 15, each comprising a flip-flop unit, such as the flip-flop unit 12. In FIG. 2, an OR gate 21 coupled to the output terminal of every flip-flop 12 is provided. When the chip testing device 11 operates, the pin of the chip outputs a logic low signal, and the test result can be determined by reading the signal S3. If the signal S3 is at logic high level, there must be at least one pin outputting an incorrect signal, and the location of this pin only can be determined by the display device 14. If the signal S3 is at logic low level, all the pins of the chip are outputting correct signals. In one embodiment, the display device 14 is a light emitting diode (LED) or any device that can represent two logic states. In FIG. 2, the testing unit 18 can select to receive the signal from the output signal of the testing unit 15 or the signal inputted by another input terminal through the multiplexer 17.
Although functional, the conventional chip testing device is limited to testing signals output at only high logic state or low logic state. Moreover, the testing result may not always be correct. For example, if one pin of the chip is coupled to the power source, VDD, the chip testing device illustrated in FIG. 1 cannot test the faulty pin. Thus, a chip testing device capable of more complex processing and advanced testing is needed.